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preliminary data this is preliminary information on a new product now in deve lopment or undergoing evaluation. details are subject to change without notice. november 2006 rev 2 1/81 1 m58bw16f M58BW32F 16 or 32 mbit (x32, boot block, burst) 3.3v supply flash memories features supply voltage ?v dd = 2.7v to 3.6v (45ns) or v dd = 2.5v to 3.3v (55ns) ?v ddq = v ddqin = 2.4v to 3.6v for i/o buffers high performance ? access times: 45 and 55ns ? synchronous burst reads ? 75mhz effective zero wait-state burst read ? asynchronous page reads M58BW32F memory organization: ? eight 64 kbit small parameter blocks ? four 128 kbit large parameter blocks ? sixty-two 512 kbit main blocks m58bw16f memory organization: ? eight 64 kbit parameter blocks ? thirty-one 512 kbit main blocks hardware block protection ?wp pin to protect any block combination from program and erase operations ?pen signal for program/erase enable irreversible modify protection (otp like) on 128 kbits: ? block 1 (bottom device) or block 72 (top device) in the M58BW32F ? blocks 2 & 3 (bottom device) or blocks 36 & 35 (top device) in the m58bw16f security ? 64-bit unique device identifier (uid) fast programming ? write to buffer and program capability optimized for fdi drivers ? common flash interface (cfi) ? fast program/erase suspend feature in each block low power consumption ? 100a typical standby current electronic signature ? manufacturer code: 0020h ? top device codes: M58BW32Ft: 8838h m58bw16ft: 883ah ? bottom device codes: M58BW32Fb: 8837h m58bw16fb: 8839h automotive device grade 3: ? temperature: ? 40 to 125c ? automotive grade certified bga lbga80 (za) 10 x 8 ball array pqfp80 (t) www.st.com
contents m58bw16f, M58BW32F 2/81 contents 1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.1 block protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2 signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.1 address inputs (a0-amax) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.2 data inputs/outputs (dq0-dq31) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.3 chip enable (e ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.4 output enable (g ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.5 output disable (gd ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.6 write enable (w ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.7 reset/power-down (rp ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.8 program/erase enable (pen) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.9 latch enable (l ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.10 burst clock (k) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.11 burst address advance (b ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.12 valid data ready (r) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.13 write protect (wp ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.14 supply voltage (v dd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.15 output supply voltage (v ddq ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.16 input supply voltage (v ddqin ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.17 ground (v ss and v ssq ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.18 don?t use (du) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 2.19 not connected (nc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3 bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.1 asynchronous bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.1.1 asynchronous bus read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.1.2 asynchronous latch controlled bus read . . . . . . . . . . . . . . . . . . . . . . 24 3.1.3 asynchronous page read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.1.4 asynchronous bus write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.1.5 asynchronous latch controlled bus write . . . . . . . . . . . . . . . . . . . . . . 25 3.1.6 output disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
m58bw16f, M58BW32F contents 3/81 3.1.7 standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.1.8 reset/power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.2 synchronous bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.2.1 synchronous burst read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.2.2 synchronous burst read suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.3 burst configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.3.1 read select bit (m15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.3.2 standby disable bit (m14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.3.3 x-latency bits (m13-m11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.3.4 y-latency bit (m9) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.3.5 valid data ready bit (m8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.3.6 wrap burst bit (m3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 3.3.7 burst length bit (m2-m0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 4 command interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 4.1 read memory array command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 4.2 read electronic signature command . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 4.3 read query command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 4.4 read status register command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 4.5 clear status register command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 4.6 block erase command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 4.7 erase all main blocks command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 4.8 program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 4.9 write to buffer and program command . . . . . . . . . . . . . . . . . . . . . . . . . . 35 4.10 program/erase suspend command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 4.11 program/erase resume command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 4.12 set burst configuration register command . . . . . . . . . . . . . . . . . . . . . . . 37 4.13 set block protection configuration register command . . . . . . . . . . . . . . 37 4.14 clear block protection conf iguration register command . . . . . . . . . . . . 37 5 status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 5.1 program/erase controller status (bit 7) . . . . . . . . . . . . . . . . . . . . . . . . . . 40 5.2 erase suspend status (bit 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 5.3 erase status (bit 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 5.4 program/ write to buffer and program status (bit 4) . . . . . . . . . . . . . . . . 41
contents m58bw16f, M58BW32F 4/81 5.4.1 pen status (bit 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 5.5 program suspend status (bit 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 5.6 block protection status (bit 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 5.7 bit 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 6 maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 7 dc and ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 8 package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 9 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 appendix a flowcharts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 appendix b common flash interface (c fi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
m58bw16f, M58BW32F list of tables 5/81 list of tables table 1. signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 2. M58BW32F top boot block addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 3. M58BW32F bottom boot block addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 4. m58bw16f top boot block addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 5. m58bw16f bottom boot block addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 6. asynchronous bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 7. synchronous burst read bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 8. burst configuration register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 9. burst type definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 table 10. commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 11. read electronic signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 12. program, erase times and endurance cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 13. status register bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 14. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 table 15. operating and ac measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 16. device capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 17. dc characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 18. asynchronous bus read ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 19. asynchronous page read ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 20. asynchronous write and latch controlled write ac characteristics . . . . . . . . . . . . . . . . . . 53 table 21. synchronous burst read ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 table 22. reset, power-down and power-up ac characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 table 23. lbga80 10 12mm - 8 10 active ball array, 1mm pitch, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 table 24. pqfp80 - 80 lead plastic quad flat pack, package mechanical data . . . . . . . . . . . . . . . . 63 table 25. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 table 26. query structure overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 table 27. cfi - query address and data output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 6 table 28. cfi - device voltage and timing specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 table 29. m58bw16f device geometry definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 table 30. m58bw16f extended query information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 table 31. M58BW32F device geometry definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 table 32. M58BW32F extended query information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 table 33. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
list of figures m58bw16f, M58BW32F 6/81 list of figures figure 1. logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 2. lbga connections (top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 3. pqfp connections (top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 4. example burst configuration x-1-1-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 5. ac measurement input/output waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 figure 6. ac measurement load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 figure 7. asynchronous bus read ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 figure 8. asynchronous latch controlled bus read ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . 47 figure 9. asynchronous chip enable controlled bus read ac waveforms . . . . . . . . . . . . . . . . . . . . 48 figure 10. asynchronous address controlled bus read ac waveforms . . . . . . . . . . . . . . . . . . . . . . . 48 figure 11. asynchronous page read ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 figure 12. asynchronous write ac waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1 figure 13. asynchronous latch controlled write ac waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 figure 14. synchronous burst read, latch enable controlled (data valid from ?n? clock rising edge) . 54 figure 15. synchronous burst read, chip enable controlled (data valid from ?n? clock rising edge) . 55 figure 16. synchronous burst read, valid address transition controlled (data valid from ?n? clock rising edge) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 figure 17. synchronous burst read (data valid from ?n? clock rising edge). . . . . . . . . . . . . . . . . . . . . 57 figure 18. synchronous burst read - valid data ready output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 figure 19. synchronous burst read - burst address advance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 figure 20. clock input ac waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 figure 21. reset, power-down and power-up ac waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 figure 22. lbga80 10 12mm - 8 10 ball array, 1mm pitch, bottom view package outline . . . . . . 61 figure 23. pqfp80 - 80 lead plastic quad flat pack, package outline . . . . . . . . . . . . . . . . . . . . . . . 63 figure 24. program flowchart and pseudo code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 5 figure 25. program suspend & resume flowchart and pseudo code . . . . . . . . . . . . . . . . . . . . . . . . . 66 figure 26. block erase flowchart and pseudo code. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 figure 27. erase suspend & resume flowchart and pseudo code . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 figure 28. power-up sequence followed by synchronous burst read . . . . . . . . . . . . . . . . . . . . . . . . 69 figure 29. command interface and program erase controller flowchart (a). . . . . . . . . . . . . . . . . . . . 70 figure 30. command interface and program erase controller flowchart (b). . . . . . . . . . . . . . . . . . . . 71 figure 31. command interface and program erase controller flowchart (c) . . . . . . . . . . . . . . . . . . . . 72 figure 32. command interface and program erase controller flowchart (d). . . . . . . . . . . . . . . . . . . . 73 figure 33. command interface and program erase controller flowchart (e). . . . . . . . . . . . . . . . . . . . 74
m58bw16f, M58BW32F description 7/81 1 description the m58bw16f and M58BW32F are 16 and 32 mbit non-volatile flash memories, respectively. they can be erased electrically at block level and programmed in-system on a double-word basis using a 2.7v to 3.6v or 2.5v to 3.3v v dd supply for the circuit and a 2.4v to 3.6v v ddq supply voltage for the input and output buffers. in the rest of the document the m58bw1 6f and M58BW32F will be referred to as m58bwxxf unless otherwise specified. the devices support asynchronous (latch controlled and page read) and synchronous bus operations. the synchronous burst read interface allows a high data transfer rate controlled by the burst clock signal, k. it is capable of bursting fixed or unlimited lengths of data. the burst type, latency and length are configurable and can be easily adapted to a large variety of system clock frequencies and microprocessors. all write operations are asynchronous. on power-up the memory defaults to read mode with an asynchronous bus. the device features an asymmetrical block architecture: the M58BW32F has an array of 62 main blocks of 512 kbits each, plus 4 large parameter blocks of 128kbits each and 8 small parameter blocks of 64 kbits each. the large and small parameter blocks are located either at the top (M58BW32Ft) or at the bottom (M58BW32Fb) of the address space. the first large parameter block is referred to as boot block and can be used either to store a boot code or parameters. the memory array organization is detailed in table 2: M58BW32F top boot block addresses and table 3: M58BW32F bottom boot block addresses . the m58bw16f has an array of 8 parameter blocks of 64kb each and 31 main blocks of 512kb each. in the m58bw16ft the parameter blocks are located at the top of the address space whereas in the m58bw16fb, they are located at the bottom. the memory array organization is detailed in table 4: m58bw16f top boot block addresses and table 5: m58bw16f bottom boot block addresses . program and erase commands are written to the command interface of the memory. an on- chip program/erase controller simplifies the process of programming or erasing the memory by taking care of all of the special operations that are required to update the memory contents. the end of a program or erase operation can be detected and any error conditions identified in the status register. the command set required to control the memory is consistent with jedec standards. erase can be suspended in order to perform either read or program in any other block, and then resumed. program can be suspended to read data in any other block, and then resumed. each block can be programmed and erased over 100,000 cycles.
description m58bw16f, M58BW32F 8/81 all blocks are protected during power-up. the m58bwxxf features five different levels of hardware and software block protection to avoid unwanted program/erase operations: write/protect enable input, wp , hardware protects a combination of blocks from program and erase operations. the blocks to be protected are configured individually by issuing a set block protection configuration register or a clear block protection configuration register command. all program or erase operations are blocked when reset, rp, is held low. a program/erase enable input, pen, is used to protect all blocks, preventing program and erase operations from affecting their data. a permanent user-enabled protection ag ainst modify operations is available: ? on one specific 128-kbit parameter block in the M58BW32F ? block 1 for bottom devices or block 72 for top devices ? on two specific 64-kbit parameter blocks in the m58bw16f ? blocks 2 & 3 for bottom devices or blocks 36 & 35 for top devices. a reset/power-down mode is entered when the rp input is low. in this mode the power consumption is reduced to the standby level, the device is write protected and both the status and burst configuration registers are cleared. a recovery time is required when the rp input goes high. a manufacturer code and a device code are available. they can be read from the memory allowing programming equipment or applications to automatically match their interface to the characteristics of the memory. finally, the m58bwxxf features a 64-bit unique device identifier (uid) which is programmed by st on the production line. it is unique for each die and can be used to implement cryptographic algorithms to improve security. information is available in the cfi area (see table 30: m58bw16f extended query information ). the memory is offered in pqfp80 (14 x 20mm) and lbga80 (1.0mm pitch) packages and it is supplied with all the bits erased (set to ?1?).
m58bw16f, M58BW32F description 9/81 figure 1. logic diagram ai13224b a0-amax (1) l dq0-dq31 v dd e v ss rp g gd v ddq w wp r k b v ssq v ddqin M58BW32F m58bw16f pen
description m58bw16f, M58BW32F 10/81 table 1. signal names a0-amax (1) 1. amax is equal to a18 in the m58b w16f, and to a19 in the M58BW32F. address inputs dq0-dq7 data input/output, command input dq8-dq15 data input/output, burst configuration register dq16-dq31 data input/output b burst address advance input e chip enable input g output enable input k burst clock input l latch enable input r valid data ready output rp reset /power-down input w write enable input gd output disable input wp write protect input v dd supply voltage v ddq power supply for output buffers v ddqin power supply for input buffers only pen program/erase enable v ss ground v ssq input/output ground nc not connected internally du don?t use as internally connected
m58bw16f, M58BW32F description 11/81 figure 2. lbga connections (top view through package) 1. ball d3 is nc in the m58bw16f and a19 in the M58BW32F. ai12854b b dq24 dq7 v ssq f v ddq dq26 dq4 v ddq e dq29 v ss dq0 dq3 d a0 nc a7 a11 a18 a17 c a1 a4 a5 a8 rp e a13 a16 b a2 a3 a6 v dd pen v dd a14 a 8 7 6 5 4 3 2 1 dq20 dq18 dq19 dq17 dq11 dq12 dq13 v ddq dq23 dq8 v ddq h g nc gd w v ddqin dq16 r g l dq14 dq15 k j a15 v ss a12 a9 a10 nc a19/ nc (1) nc dq31 dq30 dq2 dq28 dq6 dq25 v ssq dq10 dq9 dq21 wp k nc dq1 dq27 dq5 nc dq22
description m58bw16f, M58BW32F 12/81 figure 3. pqfp connections (top view through package) ai13225b 12 1 73 m58bw16f M58BW32F 53 v ddq dq24 dq25 dq18 dq17 dq16 dq19 dq20 dq21 dq22 dq23 v ddq dq29 dq26 dq30 du dq31 dq28 dq27 a2 a5 a3 a4 a0 a1 a11 v ss a12 a13 a14 a10 gd wp w du g v ss e k l nc b rp v ddq dq7 dq6 dq13 dq14 dq15 dq12 dq11 dq10 dq9 v ssq dq8 dq2 dq5 dq0 a19/nc (1) a18 a16 a17 dq3 dq4 v ssq v ssq a8 a6 a7 pen v dd a9 a15 dq1 v ddq v ssq r v dd nc v ddqin 24 25 32 40 41 64 65 80
m58bw16f, M58BW32F description 13/81 1.1 block protection the m58bwxxf features four different levels of block protection. write protect pin, wp , - when wp is low, v il , the protection status that has been configured in the block protection configuration register is activated. the block protection configuration register is volatile. any combination of blocks is possible. any attempt to program or erase a protected block will retu rn an error in the status register (see table 13: status register bits ). reset/power-down pin, rp , - if the device is held in reset mode (rp at v il ), no program or erase operation can be performed on any block. program/erase enable, pen , - the program/erase enable input, pen, protects all blocks by preventing program and erase operations from modifying the data. prior to issuing a program or erase command, the program/erase enable must be set to high (v ih ). if it is low (v il ), the program or erase operation is not accepted and an error is generated in the status register. permanent protection against modify operations - specific otp-like blocks can be permanently protected against modify operations (program/ erase): ? in the M58BW32F, a unique 128-kbit parameter block ? block 1 (01000h-01fffh) for bottom devices or block 72 (fe000h-fefffh) for top devices ? in the m58bw16f, two 64-kbit parameter blocks ? blocks 2 & 3 (01000h-01fffh) for bottom devices or blocks 36 & 35 (7e000h-7efffh) for top devices this protection is user-enabled. details of how this protection is activated are provided in a dedicated application note. after a device reset the first two kinds of block protection (wp , rp ) can be combined to give a flexible block protection. all blocks are protected at power-up.
description m58bw16f, M58BW32F 14/81 table 2. M58BW32F top boot block addresses # size (kbit) address range (1) 73 128 ff000h-fffffh 72 128 fe000h-fefffh (2) 71 128 fd000h-fdfffh 70 128 fc000h-fcfffh 69 64 fb800h-fbfffh 68 64 fb000h-fb7ffh 67 64 fa800h-fafffh 66 64 fa000h-fa7ffh 65 64 f9800h-f9fffh 64 64 f9000h-f97ffh 63 64 f8800h-f8fffh 62 64 f8000h-f87ffh 61 512 f4000h-f7fffh 60 512 f0000h-f3fffh 59 512 ec000h-effffh 58 512 e8000h-ebfffh 57 512 e4000h-e7fffh 56 512 e0000h-e3fffh 55 512 dc000h-dffffh 54 512 d8000h-dbfffh 53 512 d4000h-d7fffh 52 512 d0000h-d3fffh 51 512 cc000h-cffffh 50 512 c8000h-cbfffh 49 512 c4000h-c7fffh 48 512 c0000h-c3fffh 47 512 bc000h-bffffh 46 512 b8000h-bbfffh 45 512 b4000h-b7fffh 44 512 b0000h-b3fffh 43 512 ac000h-affffh 42 512 a8000h-abfffh 41 512 a4000h-a7fffh 40 512 a0000h-a3fffh 39 512 9c000h-9ffffh 38 512 98000h-9bfffh 37 512 94000h-97fffh 36 512 90000h-93fffh
m58bw16f, M58BW32F description 15/81 35 512 8c000h-8ffffh 34 512 88000h-8bfffh 33 512 84000h-87fffh 32 512 80000h-83fffh 31 512 7c000h-7ffffh 30 512 78000h-7bfffh 29 512 74000h-77fffh 28 512 70000h-73fffh 27 512 6c000h-6ffffh 26 512 68000h-6bfffh 25 512 64000h-67fffh 24 512 60000h-63fffh 23 512 5c000h-5ffffh 22 512 58000h-5bfffh 21 512 54000h-57fffh 20 512 50000h-53fffh 19 512 4c000h-4ffffh 18 512 48000h-4bfffh 17 512 44000h-47fffh 16 512 40000h-43fffh 15 512 3c000h-3ffffh 14 512 38000h-3bfffh 13 512 34000h-37fffh 12 512 30000h-33fffh 11 512 2c000h-2ffffh 10 512 28000h-2bfffh 9 512 24000h-27fffh 8 512 20000h-23fffh 7 512 1c000h-1ffffh 6 512 18000h-1bfffh 5 512 14000h-17fffh 4 512 10000h-13fffh 3 512 0c000h-0ffffh 2 512 08000h-0bfffh 1 512 04000h-07fffh 0 512 00000h-03fffh 1. addresses are indicated in 32-bit addressing. 2. otp block. table 2. M58BW32F top boot block addresses (continued) # size (kbit) address range (1)
description m58bw16f, M58BW32F 16/81 table 3. M58BW32F bottom boot block addresses # size (kbit) address range (1) 73 512 fc000h-fffffh 72 512 f8000h-fbfffh 71 512 f4000h-f7fffh 70 512 f0000h-f3fffh 69 512 ec000h-effffh 68 512 e8000h-ebfffh 67 512 e4000h-e7fffh 66 512 e0000h-e3fffh 65 512 dc000h-dffffh 64 512 d8000h-dbfffh 63 512 d4000h-d7fffh 62 512 d0000h-d3fffh 61 512 cc000h-cffffh 60 512 c8000h-cbfffh 59 512 c4000h-c7fffh 58 512 c0000h-c3fffh 57 512 bc000h-bffffh 56 512 b8000h-bbfffh 55 512 b4000h-b7fffh 54 512 b0000h-b3fffh 53 512 ac000h-affffh 52 512 a8000h-abfffh 51 512 a4000h-a7fffh 50 512 a0000h-a3fffh 49 512 9c000h-9ffffh 48 512 98000h-9bfffh 47 512 94000h-97fffh 46 512 90000h-93fffh 45 512 8c000h-8ffffh 44 512 88000h-8bfffh 43 512 84000h-87fffh 42 512 80000h-83fffh 41 512 7c000h-7ffffh 40 512 78000h-7bfffh 39 512 74000h-77fffh 38 512 70000h-73fffh 37 512 6c000h-6ffffh 36 512 68000h-6bfffh
m58bw16f, M58BW32F description 17/81 35 512 64000h-67fffh 34 512 60000h-63fffh 33 512 5c000h-5ffffh 32 512 58000h-5bfffh 31 512 54000h-57fffh 30 512 50000h-53fffh 29 512 4c000h-4ffffh 28 512 48000h-4bfffh 27 512 44000h-47fffh 26 512 40000h-43fffh 25 512 3c000h-3ffffh 24 512 38000h-3bfffh 23 512 34000h-37fffh 22 512 30000h-33fffh 21 512 2c000h-2ffffh 20 512 28000h-2bfffh 19 512 24000h-27fffh 18 512 20000h-23fffh 17 512 1c000h-1ffffh 16 512 18000h-1bfffh 15 512 14000h-17fffh 14 512 10000h-13fffh 13 512 0c000h-0ffffh 12 512 08000h-0bfffh 11 64 07800h-07fffh 10 64 07000h-077ffh 9 64 06800h-06fffh 8 64 06000h-067ffh 7 64 05800h-05fffh 6 64 05000h-057ffh 5 64 04800h-04fffh 4 64 04000h-047ffh 3 128 03000h-03fffh 2 128 02000h-02fffh 1 128 01000h-01fffh (2) 0 128 00000h-00fffh 1. addresses are indicated in 32-bit word addressing. 2. otp block. table 3. M58BW32F bottom boot block addresses (continued) # size (kbit) address range (1)
description m58bw16f, M58BW32F 18/81 table 4. m58bw16f top boot block addresses # size (kbit) address range 38 64 7f800h-7ffffh 37 64 7f000h-7f7ffh 36 (1) 1. otp block. 64 7e800h-7efffh 35 (1) 64 7e000h-7e7ffh 34 64 7d800h-7dfffh 33 64 7d000h-7d7ffh 32 64 7c800h-7cfffh 31 64 7c000h-7c7ffh 30 512 78000h-7bfffh 29 512 74000h-77fffh 28 512 70000h-73fffh 27 512 6c000h-6ffffh 26 512 68000h-6bfffh 25 512 64000h-67fffh 24 512 60000h-63fffh 23 512 5c000h-5ffffh 22 512 58000h-5bfffh 21 512 54000h-57fffh 20 512 50000h-53fffh 19 512 4c000h-4ffffh 18 512 48000h-4bfffh 17 512 44000h-47fffh 16 512 40000h-43fffh 15 512 3c000h-3ffffh 14 512 38000h-3bfffh 13 512 34000h-37fffh 12 512 30000h-33fffh 11 512 2c000h-2ffffh 10 512 28000h-2bfffh 9 512 24000h-27fffh 8 512 20000h-23fffh 7 512 1c000h-1ffffh 6 512 18000h-1bfffh 5 512 14000h-17fffh 4 512 10000h-13fffh 3 512 0c000h-0ffffh 2 512 08000h-0bfffh 1 512 04000h-07fffh 0 512 00000h-03fffh
m58bw16f, M58BW32F description 19/81 table 5. m58bw16f bottom boot block addresses # size (kbit) address range 38 512 7c000h-7ffffh 37 512 78000h-7bfffh 36 512 74000h-77fffh 35 512 70000h-73fffh 34 512 6c000h-6ffffh 33 512 68000h-6bfffh 32 512 64000h-67fffh 31 512 60000h-63fffh 30 512 5c000h-5ffffh 29 512 58000h-5bfffh 28 512 54000h-57fffh 27 512 50000h-53fffh 26 512 4c000h-4ffffh 25 512 48000h-4bfffh 24 512 44000h-47fffh 23 512 40000h-43fffh 22 512 3c000h-3ffffh 21 512 38000h-3bfffh 20 512 34000h-37fffh 19 512 30000h-33fffh 18 512 2c000h-2ffffh 17 512 28000h-2bfffh 16 512 24000h-27fffh 15 512 20000h-23fffh 14 512 1c000h-1ffffh 13 512 18000h-1bfffh 12 512 14000h-17fffh 11 512 10000h-13fffh 10 512 0c000h-0ffffh 9 512 08000h-0bfffh 8 512 04000h-07fffh 7 64 03800h-03fffh 6 64 03000h-037ffh 5 64 02800h-02fffh 4 64 02000h-027ffh 3 (1) 1. otp block. 64 01800h-01fffh 2 (1) 64 01000h-017ffh 1 64 00800h-00fffh 0 64 00000h-007ffh
signal descriptions m58bw16f, M58BW32F 20/81 2 signal descriptions see figure 1: logic diagram and table 1: signal names , for a brief overview of the signals connected to this device. 2.1 address inputs (a0-amax) amax is equal to a18 in the m58bw16f, and to a19 in the M58BW32F. the address inputs are used to select the cells to access in the memory array during bus operations. during bus write operations they control the commands sent to the command interface of the program/erase controller. chip enable must be low when selecting the addresses. the address inputs are latched on the rising edge of latch enable l or burst clock k, whichever occurs first, in a read operation.the address inputs are latched on the rising edge of chip enable, write enable or latch enable , whichever occurs first in a write operation. the address latch is transparent when latch enable is low, v il . the address is internally latched in an erase or program operation. 2.2 data inputs/outputs (dq0-dq31) the data inputs/outputs output the data stored at the selected address during a bus read operation, or are used to input the data during a program operation. during bus write operations they represent the commands sent to the command interface of the program/erase controller. when used to input data or write commands they are latched on the rising edge of write enable or chip enable, whichever occurs first. when chip enable and output enable are both low, v il , and output disable is at v ih, the data bus outputs data from the memory array, the electronic signature, the block protection configuration register, the cfi information or the contents of burst configuration register or status register. the data bus is high impedance when the device is deselected with chip enable at v ih , output enable at v ih , output disable at v il or reset/power-down at v il . the status register content is output on dq0-dq7 and dq8-dq31 are at v il . 2.3 chip enable (e ) the chip enable, e , input activates the memory control logic, input buffers, decoders and sense amplifiers. chip enable, e , at v ih deselects the memory and reduces the power consumption to the standby level. 2.4 output enable (g ) the output enable, g , gates the outputs through the data output buffers during a read operation, when output disable gd is at v ih . when output enable g is at v ih , the outputs are high impedance independently of output disable.
m58bw16f, M58BW32F signal descriptions 21/81 2.5 output disable (gd ) the output disable, gd , deactivates the data output buffers. when output disable, gd , is at v ih , the outputs are driven by the output enable. when output disable, gd , is at v il , the outputs are high impedance independently of output enable. the output disable pin must be connected to an external pull-up resistor as there is no internal pull-up resistor to drive the pin. 2.6 write enable (w ) the write enable, w , input controls writing to the command interface, input address and data latches. both addresses and data can be latched on the rising edge of write enable (also see latch enable, l ). 2.7 reset/power-down (rp ) the reset/power-down, rp , is used to apply a hardware reset to the memory. a hardware reset is achieved by holding reset/power-down low, v il , for at least t plph . writing is inhibited to protect data, the command interface and the program/erase controller are reset. the status register information is cleared and power consumption is reduced to the standby level (i dd1 ). the device acts as deselected, that is the data outputs are high impedance. after reset/power-down goes high, v ih , the memory will be ready for bus read operations after a delay of t phel or bus write operations after t phwl . if reset/power-down goes low, v il , during a block erase or a program operation, the operation is aborted, in a time of t plrh maximum, and data is altered and may be corrupted. during power-up power should be applied simultaneously to v dd and v ddq(in) with rp held at v il . when the supplies are stable rp is taken to v ih . output enable, g , chip enable, e , and write enable, w , should be held at v ih during power-up. in an application, it is recommended to associate the reset/power-down pin, rp , with the reset signal of the microprocessor. otherwise, if a reset operation occurs while the memory is performing an erase or program operation, the memory may output the status register information instead of being initialized to the default asynchronous random read mode. see ta bl e 2 2 and figure 21: reset, power-down and power-up ac waveform , for more details. 2.8 program/erase enable (pen) the program/erase enable input, pen, protects all blocks by preventing program and erase operations from modifying the data. prior to issuing a program or erase command, the program/erase enable must be set to high (v ih ). if it is low (v il ), the program or erase operation is not accepted and an error is generated in the status register.
signal descriptions m58bw16f, M58BW32F 22/81 2.9 latch enable (l ) the bus interface can be configured to latch the address inputs on the rising edge of latch enable, l , for asynchronous latch enable controlled read or write or synchronous burst read operations. in synchronous burst read operations the address is latched on the active edge of the clock when latch enable is low, v il . once latched, the addresses may change without affecting the address used by the memory. when latch enable is low, v il , the latch is transparent. latch enable, l , can remain at v il for asynchronous random read and write operations. 2.10 burst clock (k) the burst clock, k, is used to synchronize the memory with the external bus during synchronous burst read operations. bus signals are latched on the active edge of the clock. in synchronous burst read mode the address is latched on the first rising clock edge when latch enable is low, v il , or on the rising edge of latch enable, whichever occurs first. during asynchronous bus operations the clock is not used. 2.11 burst address advance (b ) the burst address advance, b , controls the advancing of the address by the internal address counter during synchronous burst read operations. burst address advance, b , is only sampled on the active clock edge of the clock when the x-latency time has expired. if burst address advance is low, v il , the internal address counter advances. if burst address advance is high, v ih , the internal address counter does not change; the same data remains on the data inputs/outputs and burst address advance is not sampled until the y-latency expires. the burst address advance, b , may be tied to v il . 2.12 valid data ready (r) the valid data ready output, r, can be used during synchronous burst read operations to identify if the memory is ready to output data or not. the valid data ready output can be configured to be active on the clock edge of the invalid data read cycle or one cycle before. valid data ready, at v ih , indicates that new data is or will be available. when valid data ready is low, v il , the previous data outputs remain active. 2.13 write protect (wp ) the write protect, wp , provides protection against program or erase operations. when write protect, wp , is at v il , the protection status that has been configured in the block protection configuration register is activated. program and erase operations to protected blocks are disabled. when write protect wp is at v ih all the blocks can be programmed or erased, if no other protection is used.
m58bw16f, M58BW32F signal descriptions 23/81 2.14 supply voltage (v dd ) the supply voltage, v dd , is the core power supply. all internal circuits draw their current from the v dd pin, including the program/erase controller. 2.15 output supply voltage (v ddq ) the output supply voltage, v ddq , is the output buffer power supply for all operations (read, program and erase) used for dq0-dq31 when used as outputs. 2.16 input supply voltage (v ddqin ) the input supply voltage, v ddin , is the power supply for all input signal. input signals are: k, b , l , w , gd , g , e , a0-amax and dq0-dq31, when used as inputs. 2.17 ground (v ss and v ssq ) the ground v ss is the reference for the internal supply voltage v dd . the ground v ssq is the reference for the output and input supplies v ddq, and v ddqin . it is essential to connect v ss and v ssq together. note: a 0.1f capacitor should be connected between the supply voltages, v dd , v ddq and v ddin and the grounds, v ss and v ssq to decouple the current surges from the power supply. the pcb track widths must be sufficient to carry the currents required during all operations of the parts, see table 17: dc characteristics , for maximum current supply requirements. 2.18 don?t use (du) this pin should not be used as it is internally connected. its voltage level can be between v ss and v ddq or leave it unconnected. 2.19 not connected (nc) this pin is not physically connected to the device.
bus operations m58bw16f, M58BW32F 24/81 3 bus operations each bus operations that controls the memory is described in this section, see tables 6 and 7 bus operations, for a summary. the bus operation is selected through the burst configuration register; the bits in this register are described at the end of this section. on power-up or after a hardware reset the memory defaults to asynchronous bus read and asynchronous bus write. no synchronous operation can be performed until the burst control register has been configured. the electronic signature, block protection conf iguration, cfi or stat us register will be read in asynchronous mode regardless of the burst control register settings. typically glitches of less than 5ns on chip enable or write enable are ignored by the memory and do not affect bus operations. 3.1 asynchronous bus operations for asynchronous bus operations refer to ta bl e 6 together with the following text. the read access will start at whichever of the three following events occurs last: valid address transition, chip enable, e , going low, v il or latch enable, l , going low, v il . 3.1.1 asynchronous bus read asynchronous bus read operations read from the memory cells, or specific registers (electronic signature, block protection configuration register, status register, cfi and burst configuration register) in the command interface. a valid bus operation involves setting the desired address on the address inputs, applying a low signal, v il , to chip enable and output enable and keeping write enable and output disable high, v ih . the data inputs/out puts will output the value, see figure 7: asynchronous bus read ac waveforms , and table 18: asynchronous bus read ac characteristics , for details of when the output becomes valid. asynchronous read is the default read mode which the device enters on power-up or on return from reset/power-down. 3.1.2 asynchronous latch controlled bus read asynchronous latch controlled bus read operations read from the memory cells or specific registers in the command interface. the address is latched in the memory before the value is output on the data bus, allowing the address to change during the cycle without affecting the address that the memory uses. a valid bus operation involves setting the desired address on the address inputs, setting chip enable and latch enable low, v il and keeping write enable high, v ih ; the address is latched on the rising edge of latch enable. once latched, the address inputs can change. set output enable low, v il , to read the data on the data inputs/outputs; see figure figure 8: asynchronous latch controlled bus read ac waveforms and ta b l e 1 8 : asynchronous bus read ac characteristics , for details on when the output becomes valid. note that, since the latch enable input is transparent when set low, v il , asynchronous bus read operations can be performed when the memory is configured for asynchronous latch enable bus operations by holding latch enable low, v il throughout the bus operation.
m58bw16f, M58BW32F bus operations 25/81 3.1.3 asynchronous page read asynchronous page read operations are used to read from several addresses within the same memory page. each memory page is 4 double-words and is addressed by the address inputs a0 and a1. data is read internally and stored in the page buffer. valid bus operations are the same as asynchronous bus read operations but with different timings. the first read operation within the page has identical timings, subsequent reads within the same page have much shorter access times. if the page changes then the normal, longer timings apply again. page read does not support latched controlled read. see figure 11: asynchronous page read ac waveforms , and table 19: asynchronous page read ac characteristics , for details on when the outputs become valid. 3.1.4 asynchronous bus write asynchronous bus write operations write to the command interface in order to send commands to the memory or to latch addresses and input data to program. bus write operations are asynchronous, the clock, k, is don?t care during bus write operations. a valid asynchronous bus write operation begins by setting the desired address on the address inputs, and setting chip enable, write enable and latch enable low, v il , and output enable high, v ih , or output disable low, v il . the address inputs are latched by the command interface on the rising edge of chip enable or write enable, whichever occurs first. commands and input data are latched on the rising edge of chip enable, e , or write enable, w , whichever occurs first. output enable must remain high, and output disable low, during the whole asynchronous bus write operation. see figure 12: asynchronous write ac waveform , and table 20: asynchronous write and latch controlled write ac characteristics , for details of the timing requirements. 3.1.5 asynchronous latch controlled bus write asynchronous latch controlled bus write operations write to the command interface in order to send commands to the memory or to latch addresses and input data to program. bus write operations are asynchronous, the clock, k, is don?t care during bus write operations. a valid asynchronous latch controlled bus write operation begins by setting the desired address on the address inputs and pulsing latch enable low, v il . the address inputs are latched by the command interface on the rising edge of latch enable, write enable or chip enable, whichever occurs first. commands and input data are latched on the rising edge of chip enable, e , or write enable, w , whichever occurs first. output enable must remain high, and output disable low, during the whole asynchronous bus write operation. see figure 13: asynchronous latch controlled write ac waveform , and table 20: asynchronous write and latch controlled write ac characteristics , for details of the timing requirements. 3.1.6 output disable the data outputs are high impedance when the output enable, g , is at v ih or output disable, gd , is at v il .
bus operations m58bw16f, M58BW32F 26/81 3.1.7 standby when chip enable is high, v ih , and the program/erase controller is idle, the memory enters standby mode, the power consumption is reduced to the standby level (i dd1 ) and the data inputs/outputs pins are placed in the high impedance state regardless of output enable, write enable or output disable inputs. the standby mode can be disabled by setting the standby disable bit (m14) of the burst configuration register to ?1? (see table 17: dc characteristics ). 3.1.8 reset/power-down the memory is in reset/ power-do wn mode when re set/power-down, rp , is at v il . the power consumption is reduced to the standby level (i dd1 ) and the outputs are high impedance, independent of the chip enable, e , output enable, g , output disable, gd , or write enable, w, inputs. in this mode the device is write protected and both the status and the burst configuration registers are cleared. a recovery time is required when the rp input goes high. table 6. asynchronous bus operations (1) bus operation step e g gd w rp l a0-amax dq0-dq31 asynchronous bus read (2) v il v il v ih v ih v ih v il address data output asynchronous latch controlled bus read address latch v il v ih v ih v il v ih v il address high z read v il v il v ih v ih v ih v ih x data output asynchronous page read v il v il v ih v ih v ih x address data output asynchronous bus write v il v ih xv il v ih v il address data input asynchronous latch controlled bus write address latch v il v ih xv ih v ih v il address high z write v il v ih xv il v ih v ih x data input output enable, g v il v ih v ih v ih v ih x x high z output disable, gd v il v il v il v ih v ih x x high z standby v ih xxxv ih x x high z reset/power-down x x x x v il x x high z 1. x = don?t care. 2. data, manufacturer code, device code, burst configurati on register, standby status and bl ock protection configuration register are read using the asynchronous bus read command.
m58bw16f, M58BW32F bus operations 27/81 3.2 synchronous bus operations for synchronous bus operations refer to ta b l e 7 together with the following text. the read access will start at whichever of the three following events occurs last: valid address transition, chip enable, e , going low, v il or latch enable, l , going low, v il . 3.2.1 synchronous burst read synchronous burst read operati ons are used to read from the memory at specific times synchronized to an external reference clock. the valid edge of the clock signal is the rising edge. once the flash memory is configured in bu rst mode, it is mandatory to have an active clock signal since the switching of the output buffer databus is synchronized to the rising edge of the clock. in the absence of clock, no data is output. the burst type, length and latency can be configured. the different configurations for synchronous burst read operations are desc ribed in the burst configuration register section. refer to figure 4 for examples of synchronous burst operations. a valid synchronous burst read operation begins when the burst clock is active and chip enable and latch enable are low, v il . the burst start address is latched and loaded into the internal burst address counter on the valid burst clock k edge or on the rising edge of latch enable, whichever occurs first. after an initial memory latency time, the memory outputs data each clock cycle. the burst address advance b input controls the memory burst output. the second burst output is on the next clock valid edge after the burst address advance b has been pulled low. valid data ready, r, monitors if the memory burst boundary is exceeded and the burst controller of the microprocessor needs to insert wait states. when valid data ready is low on the rising clock edge, no new data is available and the memory does not increment the internal address counter at the active clock edge even if burst address advance, b , is low. valid data ready may be configured (by bit m8 of burst configuration register) to be valid immediately at the rising clock edge. synchronous burst read will be suspe nded if burst address advance, b , goes high, v ih . if output enable is at v il and output disable is at v ih , the last data is still valid. if output enable, g , is at v ih or output disable, gd , is at v il , but the burst address advance, b , is at v il the internal burst address counter is incremented at each burst clock k rising edge. the synchronous burst read timing diagrams and ac characteristics are described in the ac and dc parameters section. see figures 14 , 17 , 18 and 19 , and ta b l e 2 1 .
bus operations m58bw16f, M58BW32F 28/81 3.2.2 synchronous burst read suspend during a synchronous burst read operation it is possible to suspend the operation, freeing the data bus for other higher priority devices. a valid synchronous burst read operation is suspended when both output enable and burst address advance are high, v ih . the burst address advance going high, v ih , stops the burst counter and the output enable going high, v ih , inhibits the data outputs. the synchronous burst read operation can be resumed by setting output enable low. 1. x = don't care, v il or v ih . 2. m15 = 0, bit m15 is in the burst configuration register. 3. r = rising edge. 3.3 burst configuration register the burst configuration register is used to configure the type of bus access that the memory will perform. the burst configuration register is set thro ugh the command interfac e and will retain its information until it is re-configured, the device is reset, or the device goes into reset/power- down mode. the burst configuration register bits are described in ta bl e 8 . they specify the selection of the burst length, burst type, burst x and y latencies and the read operation. refer to figure 4 for examples of synchronous burst configurations. 3.3.1 read select bit (m15) the read select bit, m15, is used to switch between asynchronous and synchronous bus read operations. when the read select bit is set to ?1?, bus read operations are asynchronous; when the read select but is set to ?0?, bus read operations are synchronous. on reset or power-up the read select bit is set to?1? for asynchronous accesses. 3.3.2 standby disable bit (m14) the standby disable bit, m14, is used to disable the standby mode. when the standby bit is ?1?, the device will not enter standb y mode when chip enable goes high, v ih . table 7. synchronous burst read bus operations bus operation step e g gd rp kl b a0-amax dq0-dq31 synchronous burst read (2) address latch v il v ih xv ih r (3) v il x address input read v il v il v ih v ih r (3) v ih v il data output read suspend v il v ih xv ih xv ih v ih high z read resume v il v il v ih v ih r (3) v ih v il data output burst address advance v il v ih xv ih r (3) v ih v il high z read abort, e v ih xxv ih xxx high z read abort, rp xxxv il xxx high z
m58bw16f, M58BW32F bus operations 29/81 3.3.3 x-latency bits (m13-m11) the x-latency bits are used during synchronous bus read operations to set the number of clock cycles between the address being latched and the first data becoming available. for correct operation the x-latency bits can only assume the values in table 8: burst configuration register . 3.3.4 y-latency bit (m9) the y-latency bit is used during synchronous bus read operations to set the number of clock cycles between consecutive reads. the y-latency value depends on both the x- latency value and the setting in m9. when the y-latency is 1 the data changes each clock cycle. 3.3.5 valid data ready bit (m8) the valid data ready bit controls the timing of the valid data ready output pin, r. when the valid data ready bit is ?0? the valid data ready output pin is driven low for the rising clock edge when invalid data is output on the bus. 3.3.6 wrap burst bit (m3) burst read can be confined inside the 4 double-word boundary (wrap) or overcome the boundary (no wrap). when the wrap burst bit is set to '1' the burst read does not wrap. the wrap mode is not availa ble (m3 is always ?1?). 3.3.7 burst length bit (m2-m0) the burst length bits set the maximum number of double-words that can be output during a synchronous burst read operation. burst lengths of 4 or 8 are available. table 8: burst configuration register gives the valid combinations of the burst length bits that the memory accepts. if a burst read operation (no wrap) has be en initiated the device will output data synchronously. depending on the starting address, the device activates the valid data ready output to indicate that a delay is necessary before the data is output. if the starting address is aligned to a 4 d ouble word boundary, the 8-d ouble-word burst mode will run without activating the valid data ready output. if the starting address is not aligned to a 4 double word boundary, valid data ready is activated to indicate that the device needs an internal delay to read the successive words in the array. m10, m7 to m4 are reserved for future use.
bus operations m58bw16f, M58BW32F 30/81 table 8. burst configuration register bit description value description m15 read select 0 synchronous burst read 1 asynchronous read (default at power-up) m14 standby disable 0 standby mode enabled (default at power-up) 1 standby mode disabled m13-m11 x-latency 001 3 010 4 011 5 100 6 m10 reserved m9 y-latency 0 reserved 1 one burst clock cycle (m9 is always at ?1?) m8 valid data ready 0 r valid low during valid burst clock edge. (m8 is always at ?0?) 1 reserved m7-m4 reserved m3 wrapping 0 reserved 1 no wrap (m3 is always at ?1?) m2-m0 burst length 001 4 double-words 010 8 double-words
m58bw16f, M58BW32F bus operations 31/81 figure 4. example burst configuration x-1-1-1 table 9. burst type definition start address 4 sequential 8 sequential 0 0-1-2-3 0-1-2-3-4-5-6-7 1 1-2-3-4 1-2-3-4-5-6-7-8 2 2-3-4-5 2-3-4-5-6-7-8-9 3 3-4-5-6 3-4-5-6-7-8-9-10 4 4-5-6-7 4-5-6-7-8-9-10-11 5 5-6-7-8 5-6-7-8-9-10-11-12 6 6-7-8-9 6-7-8-9-10-11-12-13 7 7-8-9-10 7-8-9-10-11-12-13-14 8 8-9-10-11 8-9-10-11-12-13-14-15 ai03841b k dq l add valid dq dq dq dq 4-1-1-1 5-1-1-1 6-1-1-1 7-1-1-1 8-1-1-1 0123456789 valid valid valid valid valid valid valid valid valid valid valid valid valid valid valid valid valid valid valid valid dq 3-1-1-1 valid valid valid valid valid valid valid
command interface m58bw16f, M58BW32F 32/81 4 command interface all bus write operations to the memory are interpreted by the command interface. commands consist of one or more sequential bus write operations. the commands are summarized in table 10: commands . refer to ta b l e 1 0 in conjunction with the text descriptions below. 4.1 read memory array command the read memory array command returns th e memory to read mode. one bus write cycle is required to issue the read memory array command and return the memory to read mode. subsequent re ad operations will output the addr essed memory array data. once the command is issued the memory remains in read mode until another command is issued. from read mode bus read commands will access the memory array. 4.2 read electronic signature command the read electronic signature command is used to read the manufacturer code, the device code, the block protection configuration register and the burst configuration register. one bus write cycle is required to issue the read electronic signature command. once the command is issued, subsequent bus read opera tions, depending on the address specified, read the manufacturer code, the device code, the block protection configuration or the burst configuration register until another command is issued; see table 11: read electronic signature . 4.3 read query command the read query command is used to read data from the common flash interface (cfi) memory area. one bus write cycle is required to issue the read query command. once the command is issued subsequent bus read operations, depending on the address specified, read from the common flash interface memory area.
m58bw16f, M58BW32F command interface 33/81 4.4 read status register command the read status register command is used to read the status register. one bus write cycle is required to issue the read status r egister command. once the command is issued subsequent bus read operations read the status register until another command is issued. the status register information is present on the output data bus (dq0-dq7) when chip enable e and output enable g are at v il and output disable is at v ih . an interactive update of the status register bits is possible by toggling output enable or output disable. it is also possible during a program or erase operation, by de-activating the device with chip enable at v ih and then reactivating it with chip enable and output enable at v il and output disable at v ih . the content of the status register may also be read at the completion of a program, erase or suspend operation. during a block erase or program command, dq7 indicates the program/erase controller status. it is valid until the operation is completed or suspended. see the section on the status register and ta b l e 1 3 for details on the definitions of the status register bits. 4.5 clear status register command the clear status register command can be used to reset bits 1, 3, 4 and 5 in the status register to ?0?. one bus write is required to issue the clear status register command. once the command is issued the memory returns to its previous mode, subsequent bus read operations continue to output the same data. the bits in the status register are sticky and do not automatically return to ?0? when a new program, erase, block protect or block unprotect command is issued. if any error occurs then it is essential to clear any error bits in the status register by issuing the clear status register command before attempting a new program, erase or resume command. 4.6 block erase command the block erase command can be used to erase a block. it sets all of the bits in the block to ?1?. all previous data in the bl ock is lost. if the block is prot ected then the er ase operation will abort, the data in the block wi ll not be changed and the status register will ou tput the error. two bus write operations are required to issue the command; the first write cycle sets up the block erase command, the second write cycle confirms the block erase command and latches the block address in the program/erase controller and starts the program/erase controller. the sequence is abor ted if the confirm command is not given and the device will output the status register data with bits 4 and 5 set to '1'. once the command is issued subsequent bus read operations read the status register. see the section on the status register for details on the definitions of the status register bits. during the erase operat ion the memory will only accept the read stat us register command and the program/erase suspend comm and. all other commands will be ignored. if pen is at v ih , the operation can be performed. if pen goes below v ih, the operation aborts, the pen status bit in the status register is set to ?1? and the command must be re- issued. typical erase times are given in ta b l e 1 2 . see appendix a , figure 26: block erase flowchart and pseudo code , for a suggested flowchart on using the block erase command.
command interface m58bw16f, M58BW32F 34/81 4.7 erase all main blocks command the erase all main blocks command is used to erase all 63 main blocks, without affecting the parameter blocks. issuing the erase all main blocks command sets every bit in each main block to '1'. all data previously stored in the main blocks are lost. two bus write cycles are required to issue the erase all main blocks command. the first cycle sets up the command, the second cycle confirms the command and starts the program/erase controller. if the confirm command is not given the sequence is aborted, and status register bits 4 and 5 are set to '1'. if the address given in the second cycle is located in a protected block, the erase all main blocks operation aborts. the data remains unchanged in all blocks and the status register outputs the error. once the erase all main blocks command has been issued, subsequent bus read operations output the status register. see the status register section for details. during an erase all main blocks operation, only the read status register command is accepted by the memory; any other command are ignored. erase all main blocks, once started, cannot be suspended. if pen is at v ih , the operation will be performed. if pen is lower than v ih the operation aborts and the status register pen bit (bit 3) is set to '1'. 4.8 program command the program command is used to program the memory array. two bus write operations are required to issue the command; the first write cycle sets up the program command, the second write cycle latches the address and data to be programmed and starts the program/erase controller. a program operation can be aborted by writing ffffffffh to any address after the program set-up command has been given. the program command is also used to program the otp block. refer to ta bl e 1 0 : commands , for details of the address. once the command is issued subsequent bus read operations read the status register. see the section on the status register for details on the definitions of the status register bits. during the program oper ation the memory will only accept the read status register command and the program/erase suspend comm and. all other commands will be ignored. if reset/power-down, rp , falls to v il during programming the op eration will be aborted. if pen is at v ih , the operation can be performed. if pen goes below v ih, the operation aborts, the pen status bit in the status register is set to ?1? and the command must be re- issued. see appendix a , figure 24: program flowchart and pseudo code , for a suggested flowchart on using the program command.
m58bw16f, M58BW32F command interface 35/81 4.9 write to buffer and program command the write to buffer and program command makes use of the device?s double word (32 bit) write buffer to speed up programming. up to eight double words can be loaded into the write buffer and programmed into the memory. four successive steps are required to issue the command. 1. one bus write operation is required to set up the write to buffer and program command. any bus read operat ions will start to output the status register after the 1st cycle. 2. use one bus write operation to write the selected memory block address (any address in the block where the values will be prog rammed can be used) along with the value n on the data inputs/outputs, where n+1 is the number of words to be programmed. the maximum value of n+1 is 8 words. 3. use n+1 bus write operations to load the address and data for each word into the write buffer. the address must be between start address and start address plus n, where start address is the first word address. 4. finally, use one bus write operation to issue the final cycle to confirm the command and start the program operation. if any address is outside the block boundaries or if the correct sequence is not followed, status register bits 4 and 5 are set to ?1? and the operatio n will abort without affecting the data in the memory array. a protected block must be unprotected using the blocks unprotect command. during a write to buffer and program opera tion the memory will only accept the read status register and the program/erase suspend commands. all other commands are ignored. if pen is at v ih , the operation will be performe d. if pen is lower than v ih the operation aborts and the status register pen bit (bit 3) is set to '1'. the status register should be cleared before re-issuing the command.
command interface m58bw16f, M58BW32F 36/81 4.10 program/erase suspend command the program/erase suspend command is used to pause a program or erase operation. the command will only be accepted during a progra m or erase operation. it can be issued at any time during a program or erase operation. the command is ignored if the device is already in suspend mode. one bus write cycle is required to issue th e program/erase suspend command and pause the program/erase controller. once the command is issued it is necessary to poll the program/erase controller status bit (bit 7) to find out when the program/erase controller has paused; no other comman ds will be accepted until the program/erase controller has paused. after the program/eras e controller has paused, the me mory will continue to output the status register until another command is issued. during the polling period between issuing the program/erase susp end command and the program/erase controller pausing it is possible for the operation to complete. once the program/erase controller status bit (bit 7) indicates that the program/erase controller is no longer active, the program suspend status bit (bit 2) or the erase suspend status bit (bit 6) can be used to determine if the operation has completed or is suspended. for timing on the delay between issuing the program/erase suspend command and the program/erase controller pausing see note 12 . during program/erase suspend the read memory array, read status register, read electronic signature, read query and program/erase resume commands will be accepted by the command interface. additionally, if the suspended operation was erase then the program, the write to buffer and program, the set/clear block protection configuration register and the program suspend commands will also be accepted. when a program operation is completed inside a block erase suspend the read memory array command must be issued to reset the device in read mode, then the erase resume command can be issued to complete the whole sequence. only the blocks not being erased may be read or programmed correctly. erase operations can be suspended in a systematic and periodical way, however, in order to ensure the effectiveness of erase operations and avoid infinite erase times, it is imperative to wait a minimum time between successive erase resume and erase suspend commands. this time, called the minimum effective erase time, is given in table 12 on page 39 . see appendix a , figure 25: program suspend & resume flowchart and pseudo code , and figure 27: erase suspend & resume flowchart and pseudo code , for suggested flowcharts on using the program/erase suspend command. 4.11 program/erase resume command the program/erase resume command can be used to restart the program/erase controller after a program/erase suspend operation has paused it. one bus write cycle is required to issue the program/erase resume command. see appendix a , figure 25: program suspend & resume flowchart and pseudo code , and figure 27: erase suspend & resume flowchart and pseudo code , for suggested flowcharts on using the program/erase suspend command.
m58bw16f, M58BW32F command interface 37/81 4.12 set burst configurat ion register command the set burst configuration register command is used to write a new value to the burst configuration register which defines the burst length, type, x and y latencies, synchronous/asynchronous read mode. two bus write cycles are required to issue the set burst configuration register command. the first cycle writes the se tup command. the sec ond cycle writes the address where the new burst configuration register content is to be written, and confirms the command. if the command is not confirmed, the sequence is aborted and the device outputs the status register with bits 4 and 5 set to ?1?. once the command is issued the memory returns to read mode as if a read memory array command had been issued. the value for the burst configuration register is always presented on a0-a15. m0 is on a0, m1 on a1, etc.; the other address bits are ignored. 4.13 set block protection configuration register command the set block protection configuration register command is used to configure the block protection configuration register to ?protected?, for a specific block. protected blocks are fully protected from program or erase when wp pin is low, v il . the status of a protected block can be changed to ?unprotected? by using the clear block protection configuration register command. at power-up, all block are configured as ?protected?. two bus operations are required to issue a set block protection configuration register command: the first cycle writes the setup command the second write cycle specifies the address of the block to protect and confirms the command. if the command is not confirmed, the sequence is aborted and the device outputs the status register with bits 4 and 5 set to ?1?. to protect multiple blocks, the set block protection configuration register command must be repeated for each block. any attempt to re-protect a block already protected does not change its status. 4.14 clear block protection configuration register command the clear block protection configuration register command is used to configure the block protection configuration register to ?unprotected?, for a specific block thus allowing program/erase operations to this block, regardless of the wp pin status. two bus operations are required to issue a clear block protection configuration register command: the first cycle writes the setup command the second write cycle specifies the address of the block to unprotect and confirms the command. if the command is not confirmed, the sequence is aborted and the device outputs the status register with bits 4 and 5 set to ?1?. to unprotect multiple blocks, the clear block protection configuration register command must be repeated for each block. any attempt to unprotect a block already unprotected does not affect its status.
command interface m58bw16f, M58BW32F 38/81 table 10. commands (1) command cycles bus operations 1st cycle 2nd cycle 3rd cycle 4th cycle op. addr. data op. addr. data op. addr. data op. addr. data read memory array 2 write x ffh read ra rd read electronic signature (2) 2 write x 90h read ida idd read status register 1 write x 70h read query 2 write x 98h read ra rd clear status register 1 write x 50h block erase 2 write 55h 20h write ba d0h erase all main blocks 2 write 55h 80h write aah d0h program any block 2 write aah 40h 10h write pa pd otp block 2 write aah 40h write pa pd write to buffer and program n+4 write aah e8h write ba n write pa pd write x d0h program/erase suspend 1 write x b0h program/erase resume 1 write x d0h set burst configuration register ?3 write x 60h write bcrh 03h read ra rd set block protection configuration register 2 write x 60h write ba 01h clear block protection configuration register 2 write x 60h write ba d0h 1. x don?t care; ra read address, rd read data, id device code, ida identifier address, idd identifier data, srd status register data, pa program address; pd program data, qa q uery address, qd query data, ba any address in the block, bcr burst configuration register value, n+1 number of words to program, ba block address. 2. the manufacturer code, the device code, the burst conf iguration register, and the bl ock protection configuration register of each block are read us ing the read electronic signature command.
m58bw16f, M58BW32F command interface 39/81 table 11. read electronic signature code device amax-a0 dq31-dq0 manufacturer all 00000h 00000020h device m58bw16ft 00001h 0000883ah m58bw16fb 00001h 00008839h M58BW32Ft 00001h 00008838h M58BW32Fb 00001h 00008837h burst configuration register 00005h bcr (1) 1. bcr = burst configuration register. block protection configuration register all sba+02h (2) 2. sba is the start address of each block. 00000000h (unprotected) 00000001h (protected) table 12. program, erase times and endurance cycles (1) 1. t a = ?40 to 125c, v dd = 2.7v to 3.6v, v ddq = 2.6v to v dd parameters m58bwxxf unit min typ max full chip program 15 20 s double word program 15 35 s 512 kbit block erase 1 2 s 256 kbit block erase 0.8 1.6 s 64 kbit block erase 0.6 1.2 s program suspend latency time 10 s erase suspend latency time 30 s minimum effective erase time (2) 2. the minimum effective erase time is defined as the minimum time required between the last erase resume command and the next erase suspend command fo r the internal flash memory program/erase controller to be able to execute its algorithm. 30 s program/erase cycles (per block) 100,000 cycles
status register m58bw16f, M58BW32F 40/81 5 status register the status register provides information on the current or previous program, erase or block protect operation. the various bits in the status register convey information and errors on the operation. they are output on dq7-dq0. to read the status register the read status register command can be issued. the status register is automatically read after program, erase, block protect, program/erase resume commands. the status register can be read from any address. the contents of the status register can be updated during an erase or program operation by toggling the output enable or output disable pins or by de-activating (chip enable, v ih ) and then reactivating (chip enable and output enable, v il , and output disable, v ih .) the device. the status register bits are summarized in table 13: status register bits . refer to ta bl e 1 3 in conjunction with the following text descriptions. 5.1 program/erase controller status (bit 7) the program/erase controller status bit indicates whether the program/erase controller is active or inactive. when the program/erase controller status bit is set to ?0?, the program/erase controller is active; when bit7 is set to ?1?, the program/erase controller is inactive. the program/erase controller status is set to ?0? immediately after a program/erase suspend command is issued until the program/erase controller pauses. after the program/erase controller pauses the bit is set to ?1?. during program and erase operations the program/erase controller status bit can be polled to find the end of the operation. the other bits in the status register should not be tested until the program/erase controller completes the operation and the bit is set to ?1?. after the program/erase controller completes its operation the erase status (bit5), program status (bit4) bits should be tested for errors. 5.2 erase suspend status (bit 6) the erase suspend status bit indicates that an erase operation has been suspended and is waiting to be resumed. the erase suspend status should only be considered valid when the program/erase controller status bit is set to ?1? (program/erase controller inactive); after a program/erase suspend command is issued the memory may still complete the operation rather than entering the suspend mode. when the erase suspend status bit is set to ?0?, the program/erase controller is active or has completed its operation; when the bit is set to ?1?, a program/erase suspend command has been issued and the memory is waiting for a program/erase resume command. when a program/erase resume command is issued the erase suspend status bit returns to ?0?.
m58bw16f, M58BW32F status register 41/81 5.3 erase status (bit 5) the erase status bit can be used to identify if the memory has failed to verify that the block has erased correctly. the erase status bit should be read once the program/erase controller status bit is high (p rogram/erase controller inactive). when the erase status bit is set to ?0?, the memory has successfully verified that the block has erased correctly. when the erase status bit is set to ?1?, the program/erase controller has applied the maximum number of pulses to the block an d still failed to verify that the block has erased correctly. once set to ?1?, the erase status bit can only be reset to ?0? by a clear status register command or a hardware reset. if set to ?1? it should be reset before a new program or erase command is issued, otherwise t he new command will appear to fail. 5.4 program/ write to buffer and program status (bit 4) the program/write to buffer and program status bit is used to identify a program failure or a write to buffer and program failure. bit4 should be read once the program/erase controller status bit is high (p rogram/erase controller inactive). when bit 4 is set to ?0? the memory has successfully verified that the device has programmed correctly. when bit 4 is set to ?1? the device has failed to verify that the data has been programmed correctly. once set to 1?, the program status bit can only be reset to ?0? by a clear status register command or a hardware reset. if set to ?1? it should be reset before a new program or erase command is issued, otherwise t he new command will appear to fail. 5.4.1 pen status (bit 3) the pen status bit can be used to identify if a program or erase operation has been attempted when pen is low, v il . when bit 3 is set to ?0? no program or erase operations have been attempted with pen low, v il , since the last clear status register command, or hardware reset. when bit 3 is set to ?1? a program or erase operation has been attempted with pen low, v il . once set to ?1?, bit 3 can only be reset by an clear status register command or a hardware reset. if set to ?1? it should be reset before a new program or erase command is issued, otherwise the new command will appear to fail.
status register m58bw16f, M58BW32F 42/81 5.5 program suspend status (bit 2) the program suspend status bit indicates that a program operation has been suspended and is waiting to be resumed. the program suspend status should only be considered valid when the program/erase controller status bi t is set to ?1? (program/erase controller inactive); after a program/ erase suspend command is is sued the memory may still complete the operation rather than entering the suspend mode. when the program suspend status bit is set to ?0?, the program/erase controller is active or has completed its operation; when the bit is set to ?1?, a program/erase suspend command has been issued and the memory is waiting for a program/erase resume command. when a program/erase resume command is issued the program suspend status bit returns to ?0?. 5.6 block protection status (bit 1) the block protection status bit can be used to identify if a program or erase operation has tried to modify the contents of a protected block. when the block protection status bit is set to ?0?, no program or erase operations have been attempted to protected blocks since the last clear status register command or hardware reset; when the block protection status bit is set to ?1?, a program or erase operation has been attempted on a protected block. once set to ?1?, the block protection status bit can only be reset low by a clear status register command or a hardware reset. if set to ?1? it should be reset before a new program or erase command is issu ed, otherwise the new co mmand will appear to fail. 5.7 bit 0 reserved bit (set to ?1?).
m58bw16f, M58BW32F status register 43/81 table 13. status register bits bit name logic level definition 7 program/erase controller status ?1? ready ?0? busy 6 erase suspend status ?1? suspended ?0? in progress or completed 5 erase status ?1? erase error ?0? erase success 4 program status, ?1? program error ?0? program success 3 pen status bit ?0? no program or erase attempted ?1? program or erase attempted 2 program suspend status ?1? suspended ?0? in progress or completed 1 erase/program in a protected block ?1? program/erase on protected block, abort ?0? no operations to protected blocks 0 reserved ?1? reserved
maximum rating m58bw16f, M58BW32F 44/81 6 maximum rating stressing the device above the ratings listed in table 14: absolute maximum ratings , may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. refer also to the stmicroelectronics sure program and other relevant quality documents. table 14. absolute maximum ratings symbol parameter value unit min max t bias temperature under bias ?40 125 c t stg storage temperature ?55 155 c v io input or output voltage ?0.6 v ddq +0.6 v ddqin +0.6 v v dd , v ddq, v ddqin supply voltage ?0.6 4.2 v
m58bw16f, M58BW32F dc and ac parameters 45/81 7 dc and ac parameters this section summarizes the operating and measurement conditions, and the dc and ac characteristics of the device. the parameters in the dc and ac characteristics tables that follow, are derived from tests performed under the measurement conditions summarized in table 15: operating and ac measurement conditions . designers should check that the operating conditions in their circuit match th e measurement conditions when relying on the quoted parameters. figure 5. ac measurement input/output waveform 1. v dd = v ddq . figure 6. ac measurement load circuit table 15. operating and ac measurement conditions parameter m58bw16f, M58BW32F units 45ns 55ns minmaxminmax supply voltage (v dd ) 2.7 3.6 2.5 3.3 v input/output supply voltage (v ddq ) 2.4 3.6 2.4 3.6 v ambient temperature (t a ) grade 3 ?40 125 ?40 125 c load capacitance (c l )3030pf clock rise and fall times 3 3 ns input rise and fall times 3 3 ns input pulses voltages 0 to v ddq 0 to v ddq v input and output timing ref. voltages v ddq /2 v ddq /2 v ai04153 v ddq v ddqin 0v v ddq /2 v ddqin /2 ai04154b out c l c l includes jig capacitance device under test
dc and ac parameters m58bw16f, M58BW32F 46/81 1. the standby mode can be disabled by setting the standby disable bit (m14) of the burst configuration register to ?1?. 2. i ddp-up is defined only during the power-up phase, fr om the moment current is applied with rp low to the moment when the supply voltage has become stable and rp is brought to high. table 16. device capacitance (1)(2) 1. t a = 25c, f = 1 mhz 2. sampled only, not 100% tested. symbol parameter test condition typ max unit c in input capacitance v in = 0v 6 8 pf c out output capacitance v out = 0v 8 12 pf table 17. dc characteristics symbol parameter test condition min typ max unit i li input leakage current 0v v in v ddq 1 a i lo output leakage current 0v v out v ddq 5 a i dd (1) supply current (random read) e = v il , g = v ih , f add = 6mhz 25 ma i ddp-up (2) supply current (power-up) 20 ma i ddb (1) supply current (burst read) e = v il , g = v ih , f clock = 75mhz 50 ma i dd1 (1) supply current (standby) e = rp = v dd 0.2v 150 a i dd2 (1) supply current (program or erase) program, erase in progress 30 ma i dd3 (1) supply current (erase/program suspend) e = v ih 150 a i dd4 (1) supply current (standby disable) 510ma v il input low voltage ?0.5 0.2v ddqin v v ih input high voltage (for dq lines) 0.8v ddqin v ddq +0.3 v v ih input high voltage (for input only lines) 0.8v ddqin 3.6 v v ol output low voltage i ol = 100a 0.1 v v oh output high voltage cmos i oh = ?100a v ddq ?0.1 v v lko v dd supply voltage (erase and program lockout) 2.2 v
m58bw16f, M58BW32F dc and ac parameters 47/81 figure 7. asynchronous bus read ac waveforms figure 8. asynchronous latch controlled bus read ac waveforms ai08921b e g l a0-a19 dq0-dq31 valid taxqx telqx telqv tavqv tglqx tglqv tehqx tehqz tghqx tghqz see also page read output tehlx tavav gd ai08922b l e g a0-a19 dq0-dq31 valid tehlx tlhll tlhax tlllh tehqx tehqz tghqx ghqz tllqv tllqx tglqx tglqv see also page read output
dc and ac parameters m58bw16f, M58BW32F 48/81 figure 9. asynchronous chip enable controlled bus read ac waveforms figure 10. asynchronous address controlled bus read ac waveforms ai13434 l e g a0-a19 dq0-dq31 valid tehlx tlhax tehqx tehqz tghqx ghqz telqx telqv tglqx tglqv see also page read output ai13435 l e g a0-a19 dq0-dq31 valid tehlx tlhax tehqx tehqz tghqx ghqz tavqv tglqx tglqv see also page read output
m58bw16f, M58BW32F dc and ac parameters 49/81 table 18. asynchronous bus read ac characteristics symbol parameter test condition m58bwxxf unit 45 55 t avav address valid to address valid e = v il , g = v il min 45 55 ns t avqv address valid to output valid e = v il , g = v il max 45 55 ns t axqx address transition to output transition l = v il , g = v il min 0 0 ns t ehlx chip enable high to latch enable transition min 0 0 ns t ehqx chip enable high to output transition g = v il min 0 0 ns t ehqz chip enable high to output hi-z g = v il max 20 20 ns t elqv (1) 1. output enable g may be delayed up to t elqv - t glqv after the falling edge of chip enable e without increasing t elqv . chip enable low to output valid g = v il max 45 55 ns t ghqx output enable high to output transition e = v il min 0 0 ns t ghqz output enable high to output hi-z e = v il max 15 15 ns t glqv output enable low to output valid e = v il max 15 15 ns t glqx output enable low to output transition e = v il min 0 0 ns t lhax latch enable high to address transition e = v il min 5 5 ns t lhll latch enable high to latch enable low min 10 10 ns t lllh latch enable low to latch enable high e = v il min 10 10 ns t llqv latch enable low to output valid chip enable low to output valid e = v il , g = v il max 45 55 ns t llqx latch enable low to output transition e = v il , g = v il min 0 0 ns t elqx chip enable low to output transition l = v il , g = v il min 0 0 ns
dc and ac parameters m58bw16f, M58BW32F 50/81 figure 11. asynchronous page read ac waveforms ai03646 a0-a1 dq0-dq31 a0 and/or a1 tavqv1 output taxqx output + 1 table 19. asynchronous page read ac characteristics (1) symbol parameter test condition m58bwxxf unit 45 55 t avqv1 address valid to output valid e = v il , g = v il max 25 25 ns t axqx address transition to output transition e = v il , g = v il min 0 0 ns 1. for other timings see table 18: asynchronous bus read ac characteristics .
m58bw16f, M58BW32F dc and ac parameters 51/81 figure 12. asynchronous write ac waveform ai13223b dq0-dq31 w rp a0-a19 e = l g input valid valid twheh valid tavwh twlwh telwl input valid sr pen twhax twhwl twhdx tdvwh twhgl twhqv tvphwh tqvvpl tqvpl tphwh rp = v dd rp = v hh read status register write cycle write cycle tavll tavav
dc and ac parameters m58bw16f, M58BW32F 52/81 figure 13. asynchronous latch controlled write ac waveform ai13222b dq0-dq31 w rp a0-a19 l g input valid valid valid tavlh input valid sr pen tlhax read status register write cycle write cycle e tlllh tllwh twhax telwl twlwh twheh twhwl twhgl twhqv tdvwh twhdx tvphwh tqvvpl tqvpl rp = v hh rp = v dd tavwh telll tavll tavav
m58bw16f, M58BW32F dc and ac parameters 53/81 table 20. asynchronous write and latch controlled write ac characteristics symbol parameter test condition m58bwxxf unit 45 55 t avav address valid toaddress valid min 45 55 t avlh address valid to latch enable high min 8 8 ns t avll address valid to latch enable low min 0 0 ns t avwh address valid to write enable high e = v il min 25 25 ns t dvwh data input valid to write enable high e = v il min 25 25 ns t elll chip enable low to latch enable low min 0 0 ns t elwl chip enable low to write enable low min 0 0 ns t lhax latch enable high to address transition min 5 5 ns t lllh latch enable low to latch enable high min 10 10 ns t llwh latch enable low to write enable high e = v il min 25 25 ns t qvvpl output valid to pen low min 0 0 ns t vphwh pen high to write enable high min 0 0 ns t whax write enable high to address transition e = v il min 0 0 ns t whdx write enable high to input transition e = v il min 0 0 ns t wheh write enable high to chip enable high min 0 0 ns t whgl write enable high to output enable low min 150 150 ns t whqv write enable high to output valid min 165 165 ns t whwl write enable high to write enable low min 20 20 ns t wlwh write enable low to write enable high e = v il min 25 25 ns t qvpl output valid to reset/power-down low min 0 0 ns
dc and ac parameters m58bw16f, M58BW32F 54/81 figure 14. synchronous burst read, latch enable controlled (data valid from ?n? clock rising edge) ai08925c dq0-dq31 a0-a19 l e g k valid tkhax n+2 n+1 n 1 0 tkhll tllkh telll tavll tkhlh tehqx tehqz tghqx tghqz tglqv setup output tkhqv note : n depends on burst x-latency.
m58bw16f, M58BW32F dc and ac parameters 55/81 figure 15. synchronous burst read, chip enable controlled (data valid from ?n? clock rising edge) ai13284 dq0-dq31 a0-a19 l e g k valid tkhax n+2 n+1 n 1 0 tkhel telkh tkhlh tehqx tehqz tghqx tghqz tglqv setup output tkhqv note : n depends on burst x-latency. b tblkh
dc and ac parameters m58bw16f, M58BW32F 56/81 figure 16. synchronous burst read, valid address transition controlled (data valid from ?n? clock rising edge) ai13285 dq0-dq31 a0-a19 l e g k valid tkhax n+2 n+1 n 1 0 tavkh tkhlh tehqx tehqz tghqx tghqz tglqv setup output tkhqv note : n depends on burst x-latency. b tblkh
m58bw16f, M58BW32F dc and ac parameters 57/81 figure 17. synchronous burst read (data valid from ?n? clock rising edge) 1. for set up signals and timing s see synchronous burst read. figure 18. synchronous burst read - valid data ready output 1. valid data ready = vali d low during valid clock edge 2. v= valid output. 3. the internal timing of r follows dq. ai04408c k n+5 n+4 n+3 n+2 n+1 n dq0-dq31 tkhqx q0 q1 q2 q3 q4 q5 setup burst read q0 to q3 tkhqv note: n depends on burst x-latency ai03649b k output (1) vvvv trlkh r v (2)
dc and ac parameters m58bw16f, M58BW32F 58/81 figure 19. synchronous burst read - burst address advance figure 20. clock input ac waveform ai03650 k q0 q1 l q2 valid g tglqv tblkh tbhkh b dq0-dq31 a0-a19 tkhkl tklkh k ai13286
m58bw16f, M58BW32F dc and ac parameters 59/81 table 21. synchronous burst read ac characteristics (1) (2) symbol parameter test condition m58bwxxf unit 45 55 f clock frequency x-latency = 3 max 40 33 mhz x-latency = 4 max 56 40 mhz x-latency = 5 or 6 max 75 56 mhz t avkh address valid to valid clock edge, e = v il , l = v il x-latency = 3 min 9 6 ns e = v il , l = v il x-latency = 4, 5 or 6 min 6 6 ns t khkl clock high time min 6 6 ns t klkh clock low time min 6 6 ns t bhkh burst address advance high to valid clock edge e = v il , g = v il , l = v ih min 8 8 ns t blkh burst address advance low to valid clock edge e = v il , g = v il , l = v ih min 8 8 ns t elkh chip enable low to valid clock edge l = v il x-latency = 3 min 9 6 ns l = v il x-latency = 4, 5 or 6 min 6 6 ns t glqv output enable low to output valid e = v il , l = v ih max 15 15 ns t khax valid clock edge to address transition e = v il min 5 5 ns t khel valid clock edge to chip enable low l = v il min 0 0 ns t khll valid clock edge to latch enable low e = v il min 0 0 ns t khlh valid clock edge to latch enable high e = v il min 0 0 ns t khqx valid clock edge to output transition e = v il , g = v il , l = v ih min 2 2 ns t llkh latch enable low to valid clock edge, e = v il x-latency = 3 min 9 6 ns e = v il x-latency = 4, 5 or 6 min 6 6 ns t rlkh valid data ready low to valid clock edge e = v il , g = v il , l = v ih min 6 6 ns t khqv valid clock edge to output valid e = v il , g = v il , l = v ih max 8 8 ns 1. data output should be read on the valid clock edge. 2. for other timings see table 18: asynchronous bus read ac characteristics .
dc and ac parameters m58bw16f, M58BW32F 60/81 figure 21. reset, power-down and power-up ac waveform ai03849b w, rp tphwl tphel tphgl e, g vdd, vddq tvdhph tphwl tphel tphgl tplph tplrh power-up reset r table 22. reset, power-down and power-up ac characteristics symbol parameter min max unit t phel reset/power-down high to chip enable low 50 ns t phqv (1) reset/power-down high to output valid 130 ns t phwl reset/power-down high to write enable low 50 ns t phgl reset/power-down high to output enable low 50 ns t plph reset/power-down low to reset/power-down high 100 ns t plrh reset/power-down low to valid data ready high 2 30 s t vdhph supply voltages high to reset/power-down high 50 s 1. this time is t phel + t avqv or t phel + t elqv .
m58bw16f, M58BW32F package mechanical 61/81 8 package mechanical in order to meet environmental requirements, st offers these devices in ecopack? packages. these packages have a lead-free second-level interconnect. the category of second-level interconnect is marked on the package and on the inner box label, in compliance with jedec standard jesd97. the maximum ratings related to soldering conditions are also marked on the inner box label. ecopack is an st trademark. ecopack specifications are available at: www.st.com . figure 22. lbga80 10 12mm - 8 10 ball array, 1mm pitch, bottom view package outline 1. drawing is not to scale. e1 e d1 d eb a2 a1 a bga-z05 ddd fd fe sd se e ball "a1"
package mechanical m58bw16f, M58BW32F 62/81 table 23. lbga80 10 12mm - 8 10 active ball array, 1mm pitch, package mechanical data symbol millimeters inches typ min max typ min max a 1.700 0.0669 a1 0.350 0.0138 a2 1.100 0.0433 b 0.500 0.0197 d 10.000 ? ? 0.3937 ? ? d1 7.000 ? ? 0.2756 ? ? ddd 0.120 0.0047 e 12.000 ? ? 0.4724 ? ? e1 9.000 ? ? 0.3543 ? ? e 1.000 ? ? 0.0394 ? ? fd 1.500 ? ? 0.0591 ? ? fe 1.500 ? ? 0.0591 ? ? sd 0.500 ? ? 0.0197 ? ? se 0.500 ? ? 0.0197 ? ?
m58bw16f, M58BW32F package mechanical 63/81 figure 23. pqfp80 - 80 lead plastic quad flat pack, package outline 1. drawing is not to scale. table 24. pqfp80 - 80 lead plastic quad flat pack, package mechanical data symbol millimeters inches typ min max typ min max a 3.400 0.1339 a1 0.250 0.0098 a2 2.800 2.550 3.050 0.1102 0.1004 0.1201 b 0.300 0.450 0.0118 0.0177 cp 0.100 0.0039 c 0.130 0.230 0.0051 0.0091 d 23.200 22.950 23.450 0.9134 0.9035 0.9232 d1 20.000 19.900 20.100 0.7874 0.7835 0.7913 d2 18.400 ? ? 0.7244 ? ? e 0.800 ? ? 0.0315 ? ? e 17.200 16.950 17.450 0.6772 0.6673 0.6870 e1 14.000 13.900 14.100 0.5512 0.5472 0.5551 e2 12.000 ? ? 0.4724 ? ? l 0.800 0.650 0.950 0.0315 0.0256 0.0374 l1 1.600 ? ? 0.0630 ? ? 0 7 0 7 n80 80 nd 24 24 ne 16 16 qfp-b d1 cp b e a2 a n l a1 e1 e2 1 d c e d2 l1 nd ne
part numbering m58bw16f, M58BW32F 64/81 9 part numbering devices are shipped from the factory with the memory content bits erased to ?1?. for a list of available options (speed, package, etc) or for further information on any aspect of this device, please contact the st sales office nearest to you. table 25. ordering information scheme example: M58BW32F t 4 t 3 t device type m58 architecture b = burst mode operating voltage w = [2.7 v to 3.6 v] v dd range for 45 ns speed class [2.5 v to 3.3 v] v dd range for 55 ns speed class [2.4 v to v dd ] v ddq range for 45 ns and 55 ns speed classes device function 32f = 32 mbit (x32), boot bl ock, burst, 0.11m technology 16f = 16 mbit (x32), boot bl ock, burst, 0.11m technology array matrix t = top boot b = bottom boot speed 4 = 45 ns 5 = 55 ns package t = pqfp80 za = lbga80: 1.0mm pitch device grade 3 = automotive grade certified (1) , ?40 to 125 c 1. qualified & characterized according to aec q100 & q003 or equivalent, advanced screening according to aec q001 & q002 or equivalent. option blank = standard packing t = tape & reel packing f = ecopack? package, tape & reel 24mm packing
m58bw16f, M58BW32F flowcharts 65/81 appendix a flowcharts figure 24. program flowchart and pseudo code 1. if an error is found, the status register must be cleared before further p/e operations. write 40h ai03850e start write address & data read status register yes no b7 = 1 yes no b3 = 0 no b4 = 0 pen invalid error (1) program error (1) program command: ? write 40h, address aah ? write address & data (memory enters read status state after the program command) do: ? read status register (e or g must be toggled) while b7 = 1 if b3 = 1, pen invalid error: ? error handler if b4 = 1, program error: ? error handler yes end no b1 = 0 program to protect block error if b1 = 1, program to protected block error: ? error handler yes
flowcharts m58bw16f, M58BW32F 66/81 figure 25. program suspend & resume flowchart and pseudo code write 70h ai00612b read status register yes no b7 = 1 yes no b2 = 1 program continues write ffh program/erase suspend command: ? write b0h ? write 70h do: ? read status register while b7 = 1 if b2 = 0, program completed read memory array command: ? write ffh ? one or more data reads from other blocks write d0h program erase resume command: ? write d0h to resume programming ? if the program operation completed then this is not necessary. the device returns to read array as normal (as if the program/erase suspend command was not issued). read data from another block start write b0h program complete write ffh read data
m58bw16f, M58BW32F flowcharts 67/81 figure 26. block erase flowchart and pseudo code 1. if an error is found, the status register must be cleared before further p/e operations. write 20h ai08623d start write block address & d0h read status register yes no b7 = 1 yes no b3 = 0 yes b4 and b5 = 1 pen invalid error (1) command sequence error erase command: ? write 20h, address 55h ? write block address (a11-a19) & d0h (memory enters read status state after the erase command) do: ? read status register (e or g must be toggled) if erase command given execute suspend erase loop while b7 = 1 if b3 = 1, pen invalid error: ? error handler if b4, b5 = 1, command sequence error: ? error handler no no b5 = 0 erase error (1) yes no suspend suspend loop if b5 = 1, erase error: ? error handler yes end yes no b1 = 0 erase to protected block error if b1 = 1, erase to protected block error: ? error handler
flowcharts m58bw16f, M58BW32F 68/81 figure 27. erase suspend & resume flowchart and pseudo code write 70h ai00615c read status register yes no b7 = 1 yes no b6 = 1 erase continues write ffh program/erase suspend command do: ? read status register while b7 = 1 (b7 = program/erase status bit) if b6 = 0, erase is completed (b6 = erase suspend status bit) read memory array command: ? write ffh ? one or more data reads from other blocks write d0h read data from another block or program erase cycle in progress write b0h erase complete write ffh read data program/erase resume command: ? write d0h to resume the erase operation the device returns to read mode as normal (as if the program/erase suspend was not issued).
m58bw16f, M58BW32F flowcharts 69/81 figure 28. power-up sequence followed by synchronous burst read ai03834 power-up or reset asynchronous read write 60h command write 03h with a15-a0 bcr inputs synchronous read bcr bit 15 = '1' set burst configuration register command: ? write 60h ? write 03h and bcr on a15-a0 bcr bit 15 = '0' bcr bit 14-bit 0 = '1'
flowcharts m58bw16f, M58BW32F 70/81 figure 29. command interface and program erase controller flowchart (a) ai03835 read elec. signature yes no 90h read status yes 70h no erase set-up yes 20h no program set-up yes 40h no clear status yes 50h no wait for command write read status read array yes d b c read cfi yes 98h no no d0h a erase command error e d
m58bw16f, M58BW32F flowcharts 71/81 figure 30. command interface and program erase controller flowchart (b) ai03836 tp program set_up yes no 48h set bcr set_up yes 60h no d tp unlock set_up yes 78h no ffh 03h no yes no e f g yes
flowcharts m58bw16f, M58BW32F 72/81 figure 31. command interface and program erase controller flowchart (c) read status 70h b erase ready no a b0h no read status yes ready no erase suspend yes read array yes erase suspended read status yes no 40h no d0h no program set_up ai03837 yes yes no yes read status c
m58bw16f, M58BW32F flowcharts 73/81 figure 32. command interface and program erase controller flowchart (d) read status 70h b program ready no c b0h no read status yes ready no program suspend read array yes program suspended read status yes no no d0h ai03838 yes no yes read status yes
flowcharts m58bw16f, M58BW32F 74/81 figure 33. command interface and program erase controller flowchart (e) b tp program ready f no read status ai03839 yes b tp unlock ready g no read status yes
m58bw16f, M58BW32F common flash interface (cfi) 75/81 appendix b common flash interface (cfi) the common flash interface is a jedec approved, standardized data structure that can be read from the flash memory device. it allows a system software to query the device to determine various electrical and timing pa rameters, density information and functions supported by the memory. the system can interface easily with the device, enabling the software to upgrade itself when necessary. when the cfi query command (rcfi) is issued the device enters cfi query mode and the data structure is read from the memory. ta bl e 2 6 , ta bl e 2 7 , ta b l e 2 8 , ta b l e 3 1 and ta bl e 3 0 show the addresses used to retrieve the data. table 26. query structure overview offset sub-section name description 00h 0020h manufacturer code st 01h 883a 8839 8838 8837 device code m58bw16ft (top) m58bw16fb (bottom) M58BW32Ft (top) M58BW32Fb (bottm) 10h cfi query identification string command set id and algorithm data offset 1bh system interface information device timing and voltage information 27h device geometry definition flash memory layout p(h) (1) 1. offset 15h defines p which points to the pr imary algorithm extended query address table. primary algorithm-specific extended query ta b l e additional information specific to the primary algorithm (optional) a(h) (2) 2. offset 19h defines a which points to the alte rnate algorithm extended query address table. alternate algorithm-specific extended query ta b l e additional information specific to the alternate algorithm (optional)
common flash interface (cfi) m58bw16f, M58BW32F 76/81 table 27. cfi - query address and data output (1) (2) 1. the x8 or byte address and the x16 or word address mode are not available. 2. query data are always presented on dq7-dq0. dq31-dq8 are set to '0'. address a0-amax data instruction 10h 51h "q" 51h; "q" query ascii string 52h; "r" 59h; "y" 11h 52h "r" 12h 59h "y" 13h 03h primary vendor: command set and control interface id code 14h 00h 15h 35h (m58bw16f) 39h (M58BW32F) primary algorithm extended query address table: p(h) 16h 00h 17h 00h alternate vendor: command set and control interface id code 18h 00h 19h 00h alternate algorithm extended query address table 1ah 00h table 28. cfi - device voltage and timing specification address a0-amax data description value 1bh 27h (1) 1. bits are coded in binary code decimal, bit7 to bi t4 are scaled in volts and bit3 to bit0 in mv. v dd min 2.7 v 1ch 36h (1) v dd max 3.6 v 1dh xxxx xxxxh reserved 1eh xxxx xxxxh reserved 1fh 04h 2 n s typical for word, dword prog 20h xxxx xxxxh reserved 21h 0ah 2 n ms, typical time-out for erase block 1 s 22h xxxx xxxxh reserved 23h xxxx xxxxh reserved 24h xxxx xxxxh reserved 25h xxxx xxxxh reserved 26h xxxx xxxxh reserved
m58bw16f, M58BW32F common flash interface (cfi) 77/81 table 29. m58bw16f device geometry definition address a0-amax data description value 27h 15h 2 n number of bytes memory size 2 mbytes 28h 03h device interface sync./async. x32 29h 00h organization sync./async. async. 2ah 00h maximum number of byte in multi-byte program = 2 n 32 bytes 2bh 00h 2ch 02h bit7-0 = number of erase block regions in device 2 2dh 1eh number (n-1) of erase blocks of identical size; n=31 31 blocks 2eh 00h 2fh 00h erase block region information x 256 bytes per erase block (64 kbytes) 512 kbits 30h 01h 31h 07h number (n-1) of erase blocks of identical size; n=8 8 blocks 32h 00h 33h 20h erase block region information x 256 bytes per erase block (8 kbytes) 64 kbits 34h 00h table 30. m58bw16f extended query information address offset address amax-a0 data (hex) description (p)h 35h 50 p query ascii string - extended table (p+1)h 36h 52 r (p+2)h 37h 49 y (p+3)h 38h 31h major revision number (p+4)h 39h 31h minor revision number (p+5)h 3ah 86h optional feature: (1=yes, 0=no) bit0, chip erase supported (0= no) bit1, suspend erase supported (1=yes) bit2, suspend program supported (1=yes) bit3, lock/unlock supported (0=no) bit4, queue erase supported (0=no) bit5, instant individual block locking (0=no) bit6, protection bits supported (0=no) bit7, page read supported (1=yes) bit8, synchronous read supported (1=yes) bit 9 reserved (p+6)h 3bh 01h synchronous read supported (p+7)h 3ch 00h (p+8)h 3dh 00h
common flash interface (cfi) m58bw16f, M58BW32F 78/81 (p+9)h 3eh 01h function allowed after suspend: program allowed after erase suspend (1=yes) bit 7-1 reserved for future use (p+a)h-(p+40)h 3fh-7fh reserved (p+41)h 80h xxxx xxxxh unique device id - 1 (16 bits) (p+42)h 81h xxxx xxxxh unique device id - 2 (16 bits) (p+43)h 82h xxxx xxxxh unique device id - 3 (16 bits) (p+44)h 83h xxxx xxxxh unique device id - 4 (16 bits) table 31. M58BW32F device geometry definition address a0-amax data description value 27h 16h 2 n number of bytes memory size 4 mbytes 28h 03h device interface sync./async. x32 29h 00h organization sync./async. async. 2ah 05h page size in bytes, 2 n 32 bytes 2bh 00h 2ch 03h bit7-0 = number of erase block regions in device 3 2dh 3dh number (n-1) of erase block regions of identical size; n = 62 62 2eh 00h 2fh 00h erase block region information x 256 bytes per erase block (64 kbytes) 512 kbits 30h 01h 31h 07h number (n-1) of erase blocks of identical size; n = 8 8 blocks 32h 00h 33h 20h erase block region information x 256 bytes per erase block (8 kbytes) 64 kbits 34h 00h 35h 03h number (n-1) of erase block of identical size; n = 4 4 blocks 36h 00h 37h 40h erase block region information x 256 bytes per erase block (16 kbytes) 128 kbits 38h 00h table 30. m58bw16f extended query information (continued) address offset address amax-a0 data (hex) description
m58bw16f, M58BW32F common flash interface (cfi) 79/81 table 32. M58BW32F extended query information address offset address amax-a0 data (hex) description (p)h 39h 50 p query ascii string - extended table (p+1)h 3ah 52 r (p+2)h 3bh 49 y (p+3)h 3ch 31h major revision number (p+4)h 3dh 31h minor revision number (p+5)h 3eh 86h optional feature: (1=yes, 0=no) bit0, chip erase supported (0= no) bit1, suspend erase supported (1=yes) bit2, suspend program supported (1=yes) bit3, lock/unlock supported (0=no) bit4, queue erase supported (0=no) bit5, instant individual block locking (0=no) bit6, protection bits supported (0=no) bit7, page read supported (1=yes) bit8, synchronous read supported (1=yes) bit 9 reserved (p+6)h 3fh 01h synchronous read supported (p+7)h 40h 00h (p+8)h 41h 00h (p+9)h 42h 01h function allowed after suspend: program allowed after erase suspend (1=yes) bit 7-1 reserved for future use (p+a)h-(p+40)h 43h-7fh reserved (p+41)h 80h xxxx xxxxh unique device id - 1 (16 bits) (p+42)h 81h xxxx xxxxh unique device id - 2 (16 bits) (p+43)h 82h xxxx xxxxh unique device id - 3 (16 bits) (p+44)h 83h xxxx xxxxh unique device id - 4 (16 bits)
revision history m58bw16f, M58BW32F 80/81 revision history table 33. document revision history date revision changes 09-jun-2006 1 initial release. 23-nov-2006 2 v pen signal renamed as pen and program/erase enable (pen) modified. continuous burst and wrap options are not available, x-latencies 7 and 8 removed (see table 8: burst configuration register and table 9: burst type definition ). notes removed below ta bl e 8 . t whqv timing modified in table 20: asynchronous write and latch controlled write ac characteristics . i dd max modified and i dd4 added to table 17: dc characteristics . t axqx modified in table 19: asynchronous page read ac characteristics . read access specified in asynchronous bus read and synchronous burst read . t avkh and t alkh added and t khqv for 55 ns modified in table 21: synchronous burst read ac characteristics . figure 9 , figure 10 , figure 18 and figure 19 added. double word program max modified and minimum effective erase time added to table 12: program, erase times and endurance cycles . all asynchronous bus read ac characteristics brought together in table 18: asynchronous bus read ac characteristics . t llel removed from ta bl e 1 8 and figure 7 . appendix b: common flash interface (cfi) modified.
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